The current state of semiconductor lithography has enabled electrical circuits on a scale which has been unthinkable even a few years ago. As semiconductor chip features shrink into the nanometer range, overall integrated circuit performance becomes limited by numerous factors among them are cross chip routes, on-chip clock skew and power and ground distribution. Moreover, as IC chips get larger with greater numbers of transistors, they require more signal routing, more I/O and more power to operate. Thus with such a large quantity of circuit elements, the challenges of delivering common signals and power to millions of circuit elements, has become a significant impediment to increasing overall chip performance.
While limited I/O IC packages can normally be easily packaged in leadframe type structures, higher I/O devices typically require more complex interconnection structures. These structures all serve to redistribute the fine pitch I/O of the IC chip to coarser pitches that are more manageable for interconnection at the next level of assembly such as when they are interconnected to a printed circuit board. While ceramic based interconnection structures are not uncommon, most users prefer reinforced organic materials for packaging ICs due to the lower dielectric constant and lower cost.
Present generation printed circuit based IC packaging technologies follow traditional design practices which typically involve the manufacture of monolithic substrates having one, two or more interconnection layers as required to redistribute the IC chip terminations to the more manageable pitch, while providing the best possible interconnection signal integrity. While there have been continuing advances to meet the needs of higher I/O devices, there remain limits to the performance potential of these solutions and it is not clear that the advances achieved will be capable of meeting the performance needs of next generation IC chips at reasonable costs and with reasonably short design cycles. For example, there are proposed solutions that involve total packaging of the IC on the wafer that include power, ground and redistribution wiring in the packaging elements that are bonded to the surface of the wafer. While attractive and offering the potential to reduce the number of I/O by managing, to a degree, the power and ground distribution inside the packaging portion of the completed structure, the manufacturing infrastructure is not yet prepared to deliver this type of solution because of the yield risks associated with assembly of a complete wafer.
Another challenge of present design practice is the management of circuit clocks which are vital to the efficient operation of the IC chip. Clock drivers are in normal practice integrated into the design of the IC chip. As such, they tend to be located in areas of convenience which often results in clock skew and timing errors that must be then addressed either using software or complex circuit routing solutions. Given the present challenges it is clear that there is opportunity and need for improvements which will address the gap between present approaches to and future requirements.